A 2.53 NEF 8-bit 10 kS/s 0.5 µm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

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This article presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants.

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15 p.

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Tasneem, Nishat Tarannum & Mahbub, Ifana March 3, 2021.

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This article is part of the collection entitled: UNT Scholarly Works and was provided by the UNT College of Engineering to the UNT Digital Library, a digital repository hosted by the UNT Libraries. It has been viewed 71 times. More information about this article can be viewed below.

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This article presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants.

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15 p.

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Abstract: This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.

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  • Electronics, 10(5), Multidisciplinary Digital Publishing Institute, March 3 2021, pp. 1-15

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  • Publication Title: Electronics
  • Volume: 10
  • Issue: 5
  • Article Identifier: 590
  • Peer Reviewed: Yes

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  • March 3, 2021

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  • Oct. 21, 2021, 11:33 a.m.

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  • Oct. 22, 2021, 10:36 a.m.

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Tasneem, Nishat Tarannum & Mahbub, Ifana. A 2.53 NEF 8-bit 10 kS/s 0.5 µm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants, article, March 3, 2021; (https://digital.library.unt.edu/ark:/67531/metadc1852326/: accessed May 25, 2024), University of North Texas Libraries, UNT Digital Library, https://digital.library.unt.edu; crediting UNT College of Engineering.

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